1. Field of the Invention
The present invention relates to delay-locked loop (DLL) circuits adapted to semiconductor devices.
The present application claims priority on Japanese Patent Application No. 2008-129638, the content of which is incorporated herein by reference.
2. Description of the Related Art
Due to increasing high-speed processing of electronic systems recently developed, it is necessary to perform high-speed data transfer between semiconductor devices installed in electronic systems, wherein semiconductor devices employ clock synchronization methods. As semiconductor memory devices, synchronous dynamic random-access memories (SDRAM) have been conventionally used and further developed into double-data-rate (DDR) SDRAM, DDR2 SDRAM, and DDR3 SDRAM which operate in synchronization with leading/trailing edges of clock pulses.
In order to establish synchronization with clock pulses, delay-locked loop (DLL) circuits have been used for synchronous dynamic random-access memories (SDRAM) so as to establish synchronization of timing between internal clock pulses and external clock pulses.
FIG. 9 shows an example of a DLL circuit in which a clock signal CK and an inverse clock signal /CK (where a slash or bar “/” indicates logical inversion) from an external device (not shown) are supplied to an initial circuit 11 and are then subjected to duty adjustment and delay adjustment, thus producing a DLL clock signal.
Along a path A shown by dotted lines, the DLL clock signal is supplied to a DQ replica circuit 15, from which a DQ replica output signal is supplied to a phase detection circuit 16 and subjected to phase comparison with the clock signal CK and the inverse clock signal /CK. The phase comparison result is fed back to a delay control circuit 13. Based on the phase comparison result output from the phase detection circuit 16, the delay control circuit 13 outputs a delay signal to a delay circuit 12 so as to adjust a delay element of the delay circuit 12.
Along a path B shown by dotted lines, the DLL clock signal is supplied to a duty detection circuit 21 and subjected to detection as to whether a duty thereof is above or below 50%. The duty detection result is fed back to a duty control circuit 22. Based on the duty detection result output from the duty detection circuit 21, the duty control circuit 22 outputs a control signal (i.e. a duty signal) to a duty adjustment circuit 23. The duty adjustment circuit 23 adjusts the duty of a clock signal output from the initial circuit 11 based on the clock signal CK and the inverse clock signal /CK in accordance with the duty signal output from the duty control circuit 22.
The delay circuit 12 performs delay adjustment so as to cancel out timing skew between the DQ replica output signal and the clock signal CK (or the inverse clock signal /CK). In addition, the duty adjustment circuit 23 performs duty adjustment such that the duty of the DLL clock signal becomes equal to or close to 50%.
The clock signal output from the initial circuit 11 is subjected to a frequency dividing process by a counter clock generation circuit 17, which thus outputs a counter clock signal to a DLL cycle counter 18. Based on the counter clock signal, the DLL cycle counter 18 generates an update clock signal for a prescribed duration, thus outputting it to the delay control circuit 13 and the duty control circuit 22. The delay control circuit 13 and the duty control circuit 22 update their operations in response to the update clock signal.
It is necessary for the DLL circuit of FIG. 9 to perform a delay-locked control for establishing synchronization between the internal clock signal and the external clock signal by way of a delay adjustment and duty adjustment with a small number of cycles during a DLL reset period; hence, it is necessary to simultaneously perform the delay adjustment and the duty adjustment. At a high input clock frequency, each pulse width of the input clock signal varies greatly due to delay adjustment during the locked-control operation, thus causing the DLL clock signal to disappear temporarily.
Since the phase detection circuit 16 and the duty detection circuit 21 trigger their operations in response to the DLL clock signal, it is very difficult to precisely detect the phase in the period in which the DLL clock signal disappears.
Repeating the phase detection and the duty detection in erroneous manners increases the number of cycles adapted to the delay-locked control and disables the delay-clocked control pursuant to prescribed technical specifications which are determined in advance. This requires manufacturers to solve the above problem due to the temporary disappearance of the DLL clock signal.
Various technologies for canceling out deviations of duties of clock signals have been developed and disclosed in various documents such as Patent Document 1.    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2002-42469
Patent Document 1 teaches a clock generation circuit which cancels out deviations of the duty of an output clock signal (causing some problems in phase control) by additionally using a simple circuit, thus achieving high-precision phase control. Specifically, a variable delay circuit is followed by a clock duty adjustment circuit and is controlled in the delay time thereof at the leading edge of a clock pulse, wherein the clock duty adjustment circuit performs adjustment at the trailing edge when the phase of the output clock signal at its leading edge matches the phase of a reference clock signal, thus identifying the duty of the output clock signal with the duty of the reference clock signal.
The present inventors have recognized that the clock generation circuit of Patent Document 1 is not designed to solve the above problem regarding the delay-locked control in which the DLL circuit fails to precisely perform phase adjustment due to erroneous detection during the disappearance period of the DLL clock signal, thus increasing the number of cycles adapted to the delay-locked control.
Due to the execution of the delay-locked control with a small number of cycles during the DLL reset period, it is necessary for the DLL circuit to simultaneously perform the delay adjustment and the duty adjustment. At a high input clock frequency, each pulse width of the input clock signal varies greatly due to delay adjustment during the delay-locked control so as to cause the disappearance period of the DLL clock signal, which makes it very difficult to precisely perform the phase detection and the duty detection.
In addition, repeating the phase detection and the duty detection in erroneous manners increases the number of cycles adapted to the delay-locked control and disables the delay-locked control pursuant to prescribed technical specifications.